an11486 greenchip ssl8516t pfc and flyback controller rev. 1 ? 17 july 2014 application note document information info content keywords greenchip, ssl8516t, pfc, flyback, high-efficiency, led driver abstract the ssl8516t is a member of the new generation of combined power factor correction (pfc) and flyback controller ics, used for efficient switched-mode power supplies (smps). the pfc enables low total harmonic distortion (thd) performance over a wide input voltage and output power range. the ssl8516t has a high level of integration allowing cost-effective design of power supplies using a mini mal number of external components. the ssl8516t is designed in a silic on-on-insulator (soi) process, enabling it to operate at a wide voltage range.
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 2 of 53 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller revision history rev date description v.1 20140717 first issue
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 3 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 1. introduction the ssl8516t is an integrated pfc and flyback controller in an so16 package. both controllers operate in quasi-resonant (qr) mode and in discontinuous conduction mode (dcm) with valley detection. they are independently switched. the pfc output power is on-time controlled fo r simplicity. sensing the phase of the mains voltage is not required. the flyback output power is current-mode controlled providing good input voltage ripple suppression. the integrated communication circuitry between the controllers does not require adjustment. remark: the voltage and current levels contained in this application note are typical values. the specification of the pin level spreading is given in the ssl8516t data sheet . remark: if a parameter value in this application note is different from the value in the applicable data sheet, the data sheet is leading. this application note describes the function ality of the ssl8516t and the adjustments required within the power converter application. the large signal parts of the pfc/flyback pow er stages and the coil/transformer design and data are not included in this application note. 2. features the greenchip features allow the design of reliable, cost-effective and efficient switched-mode power supplies (smps) using a minimal number of external components. 2.1 key features ? pfc and flyback controllers integrated in one so16 package ? pfc and flyback controllers operate at independent switching frequencies ? no external hardware required for the communication between the controllers ? high level of integration, resulting in a low external component count ? integrated mains voltage enable and brownout protection ? fast-latch reset function implemented ? power-down functionality for low standby mode power requirements 2.2 system features ? safe restart mode for system fault conditions ? high-voltage start-up current source (5 ma) ? reduction of hv current source (1 ma) in safe restart mode ? wide v cc range (13.4 v to 38 v) ? v cc undervoltage lockout protection (uvlo) ? mosfet driver voltage limited
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 4 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller ? easy control of start-up behavior and v cc circuit ? general-purpose input for latched protection ? internal ic overtemperature protection (otp) ? accurate pfc switch-on/switch-off cont rol using flyback switching frequency measurement ? one high-voltage spacer between th e hv pin and the next active pin ? open pin protection on the vinsense, vosense, pfcaux, fbctrl, and fbaux pins 2.3 pfc features ? fixed output voltage boost converter ? qr/dcm operation with valley switching ? frequency limitation at 400 khz to minimize mains current harmonics ? t on controlled ? mains input voltage compensation for control loop to achieve a good transient response ? overcurrent protection (ocp) ? soft-start and soft-stop ? open/short-circuit detection for pfc f eedback loop: no external overvoltage protection (ovp) circuit required ? adjustable pfc switch-off delay ? pfc switch-on/switch-off overriding functionality 2.4 flyback features ? fr/qr/dcm operation with valley switching ? frequency reduction (fr) with an adjustable minimum peak current and valley switching to maintain high efficiency at low output power levels ? frequency limitation (130 khz) to reduce switching losses and electromagnetic interference (emi) ? current mode controlled ? overcurrent protection ? soft-start ? accurate ovp through auxiliary winding ? time-out protection for output overloads and open feedback loop, available as safe restart protection
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 5 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 3. ssl8516t schematic figure 1 and figure 2 show the schematic diagrams of a typical application for a constant current output application. fig 1. ssl8516t schematic including emi filter and pfc part d d d ) & ; / ) 5 % ' & 3 ) & & / / 5 8 $ 3 ) & 3 ) & 3 ) & 3 ) & $ 8 ; 9 , 1 6 ( 1 6 ( * 1 ' , & 3 ) & & 2 0 3 3 ) & 7 , 0 ( 5 3 ) & ' 5 , 9 ( 5 3 ) & 6 ( 1 6 ( 9 2 6 ( 1 6 ( 5 p d l q v l q o h w & 5 & 5 5 5 , & & , & & , & & , & & , & & , & 5 5 5 5 5 4 ' ' & 5 5 5 , & , & , & 6 7 $ 5 3 ) & ) % & 6 7 $ 5 9 e x v 3 ) & l q g x f w r u f k d u j h o r r s 3 ) & l q g x f w r u g l v f k d u j h o r r s
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 6 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller fig 2. ssl8516t schematic including flyback and output part / $ 7 & + & & 4 4 5 5 5 5 5 5 5 ' , & ' 5 5 1 7 & , & & , & ) % ) % l q g x f w r u f k d u j h o r r s ) % l q g x f w r u g l v f k d u j h o r r s / ( ' f x u u h q w o r r s ' , 0 9 w r 9 , & ) % 7 ) % & 6 7 $ 5 9 e x v & , & , & & , & & & , & , & ) % $ 8 ; ) % & 7 5 / 9 & & ) % 6 ( 1 6 ( ) % ' 5 , 9 ( 5 + 9 6 + 9 8 % 5 ' 5 5 5 5 5 8 8 $ 8 8 % & & 5 5 ' 4 5 5 5 5 5 5 5 5 5 5 & & 9 u h i 9 u h i 9 u h i 9 u h i 9 r / ( ' o r d g 9 r ' 5 5 5 & ' & & ' ' 5 5 d d d
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 7 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 4. pin description 4.1 pinning diagram 4.2 pin descriptions fig 3. ssl8516t pinning diagram , & 9 & & + 9 * 1 ' + 9 6 ) % & 7 5 / 3 ) & 7 , 0 ( 5 ) % $ 8 ; ) % ' 5 , 9 ( 5 / $ 7 & + 3 ) & ' 5 , 9 ( 5 3 ) & & 2 0 3 3 ) & 6 ( 1 6 ( 9 , 1 6 ( 1 6 ( ) % 6 ( 1 6 ( 3 ) & $ 8 ; 9 2 6 ( 1 6 ( d d d table 1. ssl8516t pin description pin number pin name functional description summary 1v cc supply voltage: v trip =0.6v; v startup =22.3v; v th(uvlo) =13.4v when mains voltage is applied, the v cc pin capacitors are charged to v startup by the internal hv current source i hv . when v cc 4.9 v, the flyback delivers maximum power. the flyback enters fr mode when 0.54 v < v fbctrl < 4.0 v. the flyback driver stops switching when v fbctrl <0.54v. the built-in logic controls an internal 29 ? a current source i to(fbctrl) that is connected to the pin. i to(fbctrl) can be used to implement a time-out function for detecting an open control loop or a short circuit of the flyback output. for testing purposes, the time-out function can be disabled by connecting a 180 k ? resistor between pin fbctrl and ground. 4 fbaux input for flyback auxiliary winding for tr ansformer demagnetization detection, overvoltage protection (ovp) of the flyback, and, if necessary, mains dependent overpower protection (opp). the demagnetization detection on the fbaux pin and the valley detection on the hv pin determine the flyback switch-on timing in t he valley. a flyback ovp is detected at i fbaux >300 ? a (into the ic). internal filtering pr events false detection of an ovp. the flyback opp starts at i fbaux > 100 ? a (out of the ic).
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 8 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 5 latch general-purpose latched protection input when v cc reaches v startup , the latch pin capacitor is charged to 582 mv before the pfc and flyback controllers can be switched on. the latched protection is triggered when v latch < 494 mv. the pfc and the flyback are then switched off. the internal logic controls an internal 30.5 ? a current source i o(latch) which connects to the pin. with i o(latch) , connecting a negative temperature coefficient (ntc) resistor to the latch pin enables an optional la tching temperature protection. 6 pfccomp frequency compensation pin for the pfc control loop input for on-time modulation of the pfc gate drive signal. when pfc is off, the pfccomp pin is clamped to a low voltage of 3.32 v or 1.18 v (determined by v th(sel)clmp) on the vinsense pin) and an upper voltage of 3.75 v. 7 vinsense sense input for mains voltage the vinsense pin has several functions: ? mains voltage start level: v start(vinsense) =1.16v ? mains voltage stop level (brownout): v stop(vinsense) =0.89v ? mains voltage compensation for the pfc control-loop gain bandwidth ? fast-latch reset: v flr =0.75v ? pfccomp clamp select threshold: v th(sel)clmp =2.0v ? enter standby mode: v th(pd) =385mv ? exit standby mode: v th(pd)exit = 460 mv the v vinsense must be an averaged dc value, representing the ac line voltage. the vinsense pin is not used for sensing the phase of the mains voltage. 8 pfcaux input from an auxiliary winding of the pf c coil for demagnetization timing and valley detection to determine the pfc switch-on timing to prevent pin damage due to lighting surges, always connect a 5 k ? series resistor between the auxiliary winding and this pin. 9 vosense sense input for the pfc output voltage, open-loop and short-circuit detection: ? pfc output voltage start level v th(start)vosense =0.5v ? pfc output voltage stop level v th(stop)(vosense) =0.4v ? pfc output voltage regulation; v reg(vosense) =2.5v ? pfc soft ovp (cycle-by-cycle): v ovp(vosense) =2.62v table 1. ssl8516t pin description ?continued pin number pin name functional description summary
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 9 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 10 fbsense flyback current sense input on this pin, the sum of three vo ltages is measured. the voltages are: ? flyback current ? sense resistor ? i adj(fbsense) ? series resistance ? delay compensation voltage selecting the proper resistor values for the fbsense circuit: ? prevents or minimizes the risk of flyback transformer saturation ? allows some adjustment for switching on or switching off the pfc controller ? allows a system that operates line voltage independently v sense(fb)max = 545 mv at dv/dt = 0 mv ? s. v sense(fb)min = 232 mv at dv/dt = 0 mv/ ? s. v sense(fb)min is related to the adjustable peak current through the flyback transformer when flyback is operating in frequency reduction mode. there are two internal current sources connected to this pin: ? i start(soft)fb =60 ? a ? i adj(fbsense) =2.1 ? a the internal logic controls i start(soft)fb which is intended to implement a soft-start function for the flyback controller. the flyback driver only starts when i start(soft)fb can charge the soft-start capacitor to a voltage > 0.55 v. a mi nimum soft-start resistance of 15 k ? is required to ensure that the flyback controller is switched on. i adj(fbsense) is intended to support the switch -on/switch-off adjustment of the pfc. 11 pfcsense pfc overcurrent protection input the pfcsense pin limits the maximum peak current in the pfc transformer. it is a cycle-by-cycle protection. the pfc mosfet switches off when v pfcsense > 495 mv (at dv/dt = 0 mv/ ? s). the logic controls a 60 ? a current source i start(soft)pfc which connects to this pin. i start(soft)pfc is used to implement a soft-start and soft-stop function for the pfc to prevent audible noise. the pfc driver only starts when i start(soft)pfc can charge v pfcsense > 0.5 v. the soft-start resistance must exceed 15 k ? to ensure pfc start-up. 12 pfcdriver pfc mosfet gate-driver output 13 fbdriver flyback mosfet gate-driver output 14 pfctimer the pfc switch-on/switch-off control and timing the pfc is switched on without delay. the time r delays the switch-off of the pfc when the load of the flyback is removed or minimized. switch-off is triggered when two conditions are met: ? the filtered flyback operatin g frequency < 53 khz (fr mode only) ? v pfctimer >3v an externally applied voltage on the pfctim er pin can overrule the automatic pfc switch-on/switch-off: ? v pfctimer < 1.03 v: pfc is on ? v pfctimer >4.4v: pfc is off 15 hvs high-voltage safety spacer; not connected 16 hv high-voltage input for the internal start-up current source (to charge v cc ) and valley sensing input of the flyback valley detection input: the combination of demagnetization detection at the fbaux pin and valley detection at the hv pin determine the switch-on timing of the flyback mosfet in the valley. table 1. ssl8516t pin description ?continued pin number pin name functional description summary
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 10 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 5. system descripti on and calculation 5.1 pfc and flyback start conditions figure 4 shows the enable conditions of the pfc and the flyback during initial start-up. if start-up problems occur, chec k these conditions wit h an oscilloscope to find the cause of the problem. the conditions rely on dynamic signals (see figure 5 ). 5.2 initial start-up sequence at initial power-on, the ic has the following start-up sequence (see figure 5 ): 1. the hv current source i hv is set to 1.1 ma and the v cc pin capacitance is charged to 0.60 v to allow short-circuit detection at the v cc pin. 2. at v cc = 0.60 v, i hv set to 5 ma and the v cc pin capacitance is quickly charged to v startup . 3. at v startup , i hv is pinched off. the 30.5 ? a latch pin current source i o(latch) is switched on to charge the latch pin capacitance. the pfcsense and fbsense soft-start current sources are switched on. 4. when the latch pin capacitance is charged to 582 mv, the pfc can start switching when v vosense > 0.5 v and v vinsense >1.16v. 5. two additional conditions that must be met to enable the pfc driver are: ? the pfcsense pin soft-start capacitor is charged to 0.5 v ? the pfccomp pin capacitance is charged to either 1.19 v or 3.32 v, depending on v vinsense (v th(sel)clmp ) and i pfccomp > ? 55 ? a 6. conditions to enable the flyback driver are: ? the pfcsense pin soft-start capacitor is charged to 0.5 v ? the pfccomp pin capacitance is charged to either 1.19 v or 3.32 v, depending on v vinsense (v th(sel)clmp) and i pfccomp > ? 55 ? a 7. when flyback increases its output voltage, the auxiliary winding takes over the v cc supply. 8. if the flyback feedback loop signal is open (due to a fault), the time-out protection on pin fbctrl is triggered. both converters are switched off, v cc drops to v th(uvlo) , and the ic performs a safe rest art. during safe restart i hv is set to 1 ma to charge the v cc pin capacitance. a. pfc b. flyback fig 4. controller enable cond itions at initial start-up $ 1 ' / $ 7 & + ! p 9 3 ) & 6 ( 1 6 ( v r i w v w d u w ! 9 9 , 1 6 ( 1 6 ( ! 9 9 2 6 ( 1 6 ( ! 9 , 3 ) & & 2 0 3 ! ? $ 3 ) & v z l w f k r q v l j q d o d d d $ 1 ' ) % 6 ( 1 6 ( v r i w v w d u w ? 9 ) % & 7 5 / 9 3 ) & v z l w f k r q v l j q d o i o \ e d f n v z l w f k r q v l j q d o d d d
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 11 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 9. at v cc =v th(uvlo) , i ch(low) charges the v cc pin capacitance to v startup . the sequence is continued at step 3 above. in safe restart mode, the controller goes through the steps 3 to 9 as described in section 5.2 . the pfc and flyback soft-start capacitors can be chosen independently to set the soft-start time. fig 5. start-up, normal operation and restart sequence 9 & & / $ 7 & + 3 5 2 7 ( & 7 , 2 1 3 ) & 6 ( 1 6 ( 3 ) & ' 5 , 9 ( 5 ) % 6 ( 1 6 ( ) % ' 5 , 9 ( 5 ) % & 7 5 / 9 2 6 ( 1 6 ( 9 2 f k d u j l q j 9 & & f d s d f l w r u v w d u w l q j f r q y h u w h u v q r u p d o r s h u d w l r q s u r w h f w l r q u h v w d u w v r i w v w d u w v r i w v w d u w , + 9 9 v w d u w 9 , 1 6 ( 1 6 ( 9 w r ) % & 7 5 / 9 v w d u w x s 9 w k 8 9 / 2 9 w u l s 9 h q / $ 7 & + 9 w k v w d u w 9 2 6 ( 1 6 ( 9 , 1 6 ( 1 6 ( d d d 3 ) & & 2 0 3 9 h q 3 ) & & 2 0 3
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 12 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 5.3 v cc supply in a constant current output led driver, the output voltage can vary from v o(min) to v o(max) with a ratio of 3. the v cc is derived from the auxiliary win ding of the flyback transformer, which can cause high power dissipation in case of no-load. figure 6 shows options for v cc generation to supply the ssl8516t: ? basic application for fixed out put voltage applications (see figure 6 (a)) ? v cc application for an led driver with large v o range support (see figure 6 (b)) ? reduced standby power compared to figure 6 (b), v cc takeover in case of no-load by diode d3 (see figure 6 (c)). ? when pfc is always enabled, the bus voltage can be used as fixed reference during the primary stroke of the flyback (see figure 6 (d)). a. fixed output voltage example b. linear regulator example c. takeover by d3 at v o =v o(max) d. using primary stroke with pfc always on fig 6. v cc supply circuit diagrams d d d 7 ' ' ' 5 & & 5 & 9 r ) % $ 8 ; 9 & & d d d 7 ' ' ' 5 & & & 5 ' 9 5 4 & 9 r ) % $ 8 ; 9 & & d d d 7 ' ' ' ' 5 & & & 5 ' 9 5 4 & 9 r ) % $ 8 ; 9 & & d d d 7 ' ' ' 5 & & 5 & 9 r ) % $ 8 ; 9 & &
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 13 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 5.4 mains voltage sensing and brownout the vinsense pin senses the mains input voltage. when v vinsense >v start(vinsense) and all the other start conditions are met (see section 5.1 ), the pfc starts switching. when v vinsense t on(fb)max is triggered. when this protection is triggered, the ic stops switching and enters safe restart mode. v vinsense must be an average dc value, representing the mains input voltage. the system works optimally using a time constant of approximately 150 ms for the vinsense pin rc filter. 5.4.1 discharging the mains input capacitor for safety reasons, dischar ge the electromagnetic comp atibility (emc) input filter x-capacitors cx with a time constant of ? <1s. the replacement resistor r v and cx determine the time constant. (1) rv can be calculated with equation 2 : (2) where: ? r1 = r2 fig 7. vinsense circuit d d d & ; p d l q v l q o h w ) / ) & & 5 5 5 5 5 % ' , & 9 , 1 6 ( 1 6 ( ? vinsense r v cx ? = r v r1 r1 r5 r9 r14 ++ ?? ? r1 r5 r9 r14 +++ ---------------------------------------------------- - +=
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 14 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 5.4.2 brownout voltage adjustment the rectified input voltage is measured using resistors r1 and r2. r1 must be equal to r2. the average rectified line voltage is calculated with equation 3 : (3) the brownout level is calculated with equation 4 : (4) where: ? v stop(vinsense) =0.89v ? v bo is the rms ac mains voltage at which the pfc converter stops at a brownout threshold of 68 v (ac) and in compliance to iec-60950 chapter 2.1.1.7 discharge of capacitors in equipment (ref. 3). example values are shown in ta b l e 2 . 3.3 ? f for capacitor c6 and 47 k ? for resistor r14, sets the recommended ~150 ms time constant for the vinsense pin filter. 5.5 internal overtemper ature protection (otp) the ic has an internal temperature protection to protect the ic from overheating. the ic stops switching when the junction temperature exceeds the thermal shutdown temperature. as long as the otp is active, the v cc capacitor is not recharged from the hv mains. when the v cc supply voltage is not sufficient, the otp circuit is supplied from the hv pin. the internal otp is not a latched prot ection. a safe restart is performed when the internal otp is released. 5.6 latch pin the latch pin is a general-purpose input pin which can be used to disable and latch both converters. the pin sources a bias current i o(latch) of 30.5 ? a for the connection of an ntc resistor. when v latch an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 15 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller latching on application overtemperature occurs when r otp < 16.2 k ? . (5) where: ? r otp is r28 + r35 5.7 fast latch reset a power cycle (switch-off/switch-on) resets t he latched protection. after the input voltage is switched off, v vinsense decreases. when v vinsense (v flr +v flr(hys) ). the system restarts when the v cc pin is charged to v startup . fig 8. usage of the latch pin protection , & / $ 7 & + & 5 5 d d d * 1 ' r otp v prot latch ?? i olatch ?? ------------------------------- 494 mv 30.5 ? a ------------------- - 16.2 k ? ===
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 16 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 6. pfc description the pfc controller operates in either qr mo de or dcm mode with valley detection to reduce the switch-on losses. the maximum switching frequency f sw(pfc)max of the pfc is limited to 400 khz. one or more valleys are skipped to keep the frequency below f sw(pfc)max . the pfc is designed as a fixed boost co nverter. the resistors connected to the vosense pin set the pfc output voltage. the pfc is switched off automatically with a delay (default pfctimer pin application) to ensure high efficiency at low output curren ts. the switch off delay prevents audible noise caused by pwm / dynamic loads. after switch -off, the electrolytic bus capacitor voltage v bus drops to the peak of the mains voltage. 6.1 pfc output voltage and voltage control the pfc control in the ssl8516t is on-time controlled. the ic does not require mains phase angle sensing. to obtain a good powe r factor (pf), total harmonic distortion (thd), and a class-c mains harmonics reduct ion (mhr), the on-time is kept constant during the half sine wave. the vosense pin senses the pfc output voltage. the pin is the input of a transconductance error amplifier with a reference voltage of v reg(vosense) . the error signal (2.5 v ? v vosense ) amplified by 77 ? a/v (g m ) to a current in the pfccomp pin. v pfccomp and v vinsense determine the pfc on-time.
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 17 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller r13, c8, and c7 at the pfcc omp pin are intended to stabilize the pfc control loop. the equation for a boost converter transfer func tion contains the square of the mains input voltage. in competitor cont rollers without main s compensation, the result is a low regulation bandwidth for low mains input voltages and a high regulation bandwidth for high input voltages. the result can be that at high mains input voltages , it is difficult to meet the mhr requirements. the ssl8516t uses the mains input voltage measured through the vinsense pin to compensate t he control loop gain as a function of the mains input voltage. as a result the gain is constant over the entire mains input voltage range. v vinsense must be an average dc value, representing the mains input voltage. the system works optimally with a time constant of ~150 ms on the vinsense pin rc filter. during low-power mode operation and start-up, the pfccomp pin is clamped to a minimum voltage of 3.32 v or 1.18 v and a maximum voltage of 3.75 v. the minimum clamp voltage depends on v th(sel)clmp on the vinsense pin. this clamp limits the maximum power that is delivered when the pfc switches on. the maximum clamp voltage ensures that the pfc re turns from low-power mode to its normal regulation point in a limited time. fig 9. pfc converter on-time control 9 , 1 6 ( 1 6 ( , & 9 2 6 ( 1 6 ( 9 , 7 5 $ 1 6 ' 8 & ( 5 , 9 0 , g f k , f k 5 4 6 3 ) & ' 5 , 9 ( 5 3 ) & 2 6 & , / / $ 7 2 5 9 r v f 9 $ / / ( < ' ( 7 ( & 7 , 2 1 3 ) & $ 8 ; y r o w d j h f r p s d u d w r u u d p s r v f l o o d w r u w r q o l p l w l q j f l u f x l w , 2 3 ) & & 2 0 3 3 ) & & 2 0 3 f r p s h q v d w l r q q h w z r u n & & 5 9 u h j 9 2 6 ( 1 6 ( j p f x u u h q w p x o w l s o l h u , , 9 s & 6 d d d
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 18 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 6.2 mains current harmonics (mhr) for lighting applications, th e mains current harmonics m hr must comply with class c requirements of iec 61000-3-2. it is important to achieve a good thd over a wide input voltage range and output power range. there are multiple causes why the mains current is distorted. 6.2.1 residual c1 voltage residual voltage on capacitor c1 can cause t he diode bridge current to stop. the residual voltage depends on the load and the value of the capacitance (c1 + c2) after the bridge diode. light load conditions leave more energy in the c1 capacitor. (6) where: ? v mains(t) is the momentary mains voltage ? v f(bridge) is the forward voltage of a bridge diode 6.2.2 pfc inductor energy too low near the mains voltage, zero crossing, the energy in the pfc inductor is not sufficient to charge the q1 drain capacitance and transfer energy to the bus capacitor c4. certain offset energy in the pfc inductor is required. (7) fig 10. mhr optimization d d d p d l q v l q o h w i l q h w x q h 5 d q g 5 z l w k d q d g m x v w d e o h u h v l v w r u ) & ; & & & & 5 5 / ) / / % ' & & ' 9 e x v 5 5 4 5 5 & & 9 , 1 6 ( 1 6 ( 5 5 5 3 ) & & 2 0 3 * 1 ' , & v mains t ?? 2v fbridge ?? ? v c1 t ?? ? + 1 2 -- - l pfc i pk pfc ?? 2 ?? 1 2 -- - c d pfc ?? v bus 2 ?? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 19 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller where: ? l pfc is the pfc inductance ? i pk(pfc) is the peak current set by the actual pfc on-time ? c d(pfc) is the total capacitance on the drain of q1 (c oss +c stray ) ? v bus is the actual bus voltage 6.2.3 bus voltage ripple the bus voltage ripple with a frequency of 2 ? f ac causes a modulation of the t on(pfc) because of the vosense pin error amplifier. the 2 ? f ac ripple voltage is out of phase with the mains current, causing the mains current to be slightly asymmetrically distorted. 6.2.4 valley hopping at the maximum pfc frequency of 400 khz, the pfc controller enters dcm and it starts valley hopping. when the pfc controller transi ts from the first valley to the second, the mains current drops because the pfcdriver duty cycle decreases with a discrete step. this discrete step increases the thd. 6.2.5 mhr improvement guidelines in order to improve the thd, the following measures must be taken: ? the total capacitance (c1 + c2) after the bridge must be small to minimize residual voltage. ? to reduce capacitance after the bridge, consider to move the differential mode emi pi filter (c1, l1, c2) before the bridge diodes. ? to modulate t on(pfc) , add capacitor c5 in the circuit. as a consequence i pk(pfc) from equation 7 increases near the zero crossing and energy is transferred to c4. ? the pfc nmost drain capacitance c d(pfc) must be minimal ? choose a relatively slow pfccomp time constant (10 hz) for minimum distortion from the 2 ? f ac bus voltage ripple. ? to use the full frequency operating range of the pfc controller, choose the highest possible for l pfc . move the valley hopping angle towards the zero crossings. the frequency at low mains and high mains must not cause ringing of the emi filter.
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 20 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 6.3 pfc output voltage the pfc output voltage v bus(avg)pfcon is set using a resistor divider between v bus and the vosense pin. in normal operation mode, v bus is regulated so that v vosense equals v reg(vosense) at 2.5 v. the vosense pin has an integrated protection circuit and current i prot(vosense) to detect an open circuit pin. the bus electrolytic capacitor voltage v bus(avg)pfcon can be calculated with equation 8 : (8) where: ? i prot(vosense) = 25 na is neglected ? r15 advised < 120 k ? the pfc converter only operates nicely when: (9) always keep the bus voltage ripple below the bus capacitors voltage rating. capacitor c10 filters noise and prevents fals e triggering of protection modes because of mosfet switching noise. false triggering of the v ovp(vosense) protection can cause audible noise and disturbance of the ac mains input current. a time constant between 500 ? s and 1 ms at the vosense pin is sufficient: (10) place resistors r15 and r12 and capacitor c 10 as close as possible to pin vosense. use the ic gnd for resistor r15 and capacitor c10. fig 11. pfc output voltage setting q $ 9 2 6 ( 1 6 ( * 1 ' , & & 3 ) & v w d j h ' & 9 e x v 5 5 3 o d f h & 5 d q g 5 d v f o r v h d v s r v v l e o h w r s l q 9 2 6 ( 1 6 ( 5 d d d v bus avg ?? pfcon v reg vosense ?? r4 r12 r15 ++ r15 --------------------------------------- 1 + ?? ?? 2.5 r4 r12 r15 ++ r15 --------------------------------------- 1 + ?? ?? == v bus avg ?? pfcon v mains rms ?? 210 v + ? ? 500 ? s r15 c10 ? 1 ms ??
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 21 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the ovp level is 5 % above re gulation level which allows th e average bus voltage to be close to the voltage rating of the capacitor. however, the allowed ripple on the bus capacitor is limited because of the ovp le vel. the minimum bus capacitor value is: (11) 6.4 calculation of the pf c soft-start components soft-start and soft-stop are implemented usin g the r8 and c3 network that is connected to the pfcsense pin. to enable pfc start-up, the total series resistance must be > 15 k ? , so v start(soft)pfc = 0.5 v is reached. (12) the total soft-start time or soft-stop time is: (13) the pfctimer pin switching off pfc always en ds with a soft-stop. however, there is an exception to this rule: no soft-stop occurs when v ovp(vosense) is triggered. keep t start(soft)pfc within a range between 2 ms and 5 ms: (14) 6.5 pfc demagnetizati on and valley detection the pfc mosfet is switched on after the pfc transformer is demagnetized. the internal circuitry connected to the pfcaux pin detects the end of the secondary stroke. it also detects the voltage across the pfc mo sfet. the next primary stroke is started when the voltage across the pfc mosfet is at its minimum level. switching at the minimum voltage level (valley switchin g) reduces switching losses and emi. the maximum switching frequency of the pfc converter is limited to 400 khz. one or more valleys are skipped to keep the frequency < 400 khz. c4 min v omax ?? i omax ?? ? 4 ? f ac min ?? v bus avg ?? pfcon 2 ? total ?? ? ? ---------------------------------------------------------------------------------------------- v reg vosense ?? v ovp vosense ?? v reg vosense ?? ? ----------------------------------------------------------------------------- ? = fig 12. pfc soft-start and soft-stop 6 2 ) 7 6 7 $ 5 7 6 2 ) 7 6 7 2 3 & 2 1 7 5 2 / 2 & 3 3 ) & 6 ( 1 6 ( 9 , v w d u w v r i w 3 ) & ? $ 4 5 5 & 5 & d d d , & r7 r8 r11 15 k ?? ++ v start soft ?? pfc r8 c3 ? = 2 ms r8 c3 ? 5 ms ??
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 22 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller when the pfcaux pin does not detect demagnetization, the controller generates a zero-current signal (zcs) 48 ? s (= t to(demag)pfc ) after the last pfc gate signal. when a valley signal is not detected on this pin, the controller generates a valley signal 4.2 ? s (= t to(vrec)pfc ) after demagnetization was detected. 6.5.1 pfcaux winding and circuit design v pfcaux must be as close as possible to the absolute maximum voltage rating of ? 25 v of the pfcaux pin. this sett ing ensures valley detection at low ringing amplitudes. the maximum number of turns of the pfcaux winding is calculated with equation 15 : (15) where: ? v pfcaux(max) is the absolute maximum rating of the pfcaux pin ( ? 25 v) ? v l(pfc)max is the maximum voltage across the pfc primary winding ? n p(pfc) is the number of turns of the pfc primary winding the pfc output voltage v bus during the pfc ovp conditions determines the maximum voltage across the pfc primary winding and is calculated with equation 16 : (16) where: ? v bus(avg)pfcon is the average bus voltage when the pfc is enabled place a resistor voltage divider between t he auxiliary winding and the pfcaux pin when a pfc coil with a higher number of auxiliary turn s is used. the total resistive value of the divider must be < 10 k ? to prevent a valley detection delay due to parasitic capacitance. fig 13. pfcaux circuitry d d d & & / / 5 5 5 5 ' 4 ' & 3 ) & $ 8 ; * 1 ' 3 ) & ' 5 , 9 ( 5 9 e x v , & n aux pfc ?? v pfcaux max ?? v l pfc ?? max ---------------------------------- - n p pfc ?? ? ? v l pfc ?? max v ovp vosense ?? v reg vosense ?? ----------------------------------- - v bus avg ?? pfcon 2.62 v 2.5 v --------------- - v bus avg ?? pfcon ? = ? = 1.048 v bus avg ?? pfcon ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 23 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the polarity of the signal at the pfcaux pin is reversed compared to the pfc mosfet drain signal. to protect against electrical overstress du ring lightning surge events, always add a 5 k ? resistor between the pfc auxiliary winding and the pfcaux pin. to prevent incorrect valley switching of the pfc because of external disturbances, place th e resistor as close as possible to the ic. 6.6 pfc on/off the advantages of pfc on/off functionality are: ? disabled: improvement of overall efficiency at low output power ? enabled: improvement of power factor and harmonics of the line current in fr mode, the auto pfc on/off control mainly depends on f sw(fb) . f sw(fb) is a result of: ? primary flyback inductance ? output power ? output voltage figure 14 shows the conditions to switch on/off the pfc (fr mode only). the application can overrule the automatic pfc on/off (see section 6.6.1.2 ). remark: v vinsense 3.75 v overrules this condition. fig 14. automatic pfc on/off state transition d d d v w d u w 3 ) & r q 3 ) & r i i i v z i e n + ] w r i i i e ! ? v
i v z i e n + ] 9 ) % & 7 5 / ! 9 / ) % ' 5 , 9 ( 5 ! w r q i e ! ? v l pfb ?? max = 1 2p o pfc ?? swon f sw fb ?? swon pfc ?? ?? ? fb -------------------------------------------------------------------------------- ?? ?? 1 v bus min ?? pfcoff ------------------------------------- 1 n fb v o -------------- + ?? ?? f sw fb ?? swon pfc ?? ? c dfb ?? + 2 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 24 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller where: ? f sw(fb)swon(pfc) is 73 khz ? ? fb is the flyback controller efficiency, typically 0.95 ? v bus(min)pfcoff is the minimum mains voltage (ac) when the pfc is off ? n fb is flyback turns ratio n p(fb) /n s(fb) ? v o is the output voltage ? p o(pfc)swon is the output power at which the pfc must be enabled ? c d(fb) is the total capacitance on the drain of the flyback switch in a typical led driver, the v o varies from v o(min) to v o(max) . f sw(fb)swon(pfc) is lower at v o(min) because of the longer t off(fb) time. n fb v o(min) must be used in equation 17 . if the pfc is off, the peak of v mains(min) must trigger pfc on transition. in figure 15 the expected bus voltage waveform is shown for p o(pfc)swon at v mains(rms)min =85v(ac). substitution of the known variables results in equation 18 for l p(fb)max . (18) where: ? v mains(rms)min is the minimum rms mains voltage (ac) ? v o(min) is the minimum output voltage the primary inductance must be: (19) fig 15. v bus(min) waveform with pfc disabled at p o(pfc)swon w l p h p v d d d _ 9 p d l q v p l q _ 9 e x v p l q l pfb ?? max = 1 273 khz p opfc ?? on ?? ? fb ------------------------------------------------------ ?? ?? ?? 1 v mains rms ?? min 2 ------------------------------------------ 1 n fb v omin ?? ------------------------- - + ?? ?? ?? 73 khz ? c dfb ?? ?? + ? 2 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- l pfb ?? l pfb ?? max ?
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 25 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 6.6.1 pfctimer pin circuit when the output power drops to below the pfc switch-off level, the pfctimer pin delays the pfc switch-off. the switch-off delay prevents that the pfc repeatedly switches on and off due to fast, large, dynamic load changes. it results in reduced audible noise. different pin applications can overrule the pfctimer pin switching on/off automatically. 6.6.1.1 automatic pfc on/off the default application of the ssl8516t e nables automatic pfc on/off functionality. a capacitor connected to an internal curren t source determines the pfc switch-off delay time t d(pfc)swoff . capacitor c9 is charged from 0 v to 3 v during the de lay time. the pfc typically switches off us ing a soft-stop when v pfctimer >3v. equation 20 shows how to calculate t d(pfc)swoff : (20) where: ? the pfctimer capacitor c9 must be > 1 nf when the pfc is switched on, the ic discharges capacitor c9. an output power below the p o(pfc)swoff level for a short time results in the charging of capacitor c9. however, if v pfctimer remains under 3 v, the capacitor immediately discharges when p o >p o(pfc)swoff . the pfcdriver signal operates continuously during these load changes at the output (see figure 17 ). when p o p o(pfc)swon , the pfc switches on immediately and capacitor c9 is discharged. fig 16. pfctimer pin circuit d d d ? $ o r z s r z h u 5 6 4 9 9 3 ) & 7 , 0 ( 5 & 9 5 6 4 n
o r z s r z h u g h o d \ 3 ) & r q t dpfc ?? swoff c9 v stop pfctimer ?? i source pfctimer ?? ------------------------------------------- - c9 3 v 4.7 ? a ---------------- - ==
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 26 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 6.6.1.2 overruling automatic pfc on/off the pfc controller is typically switched on or switched off using the filtered flyback operating frequency. however, if necessary, the pfctimer allows override of this functionality. the conditions for overruling the pfctimer are: ? v pfctimer <1.0v: pfc is on ? v pfctimer >4.4v: pfc is off for applications that require the pfc to be on all the time, a 0 ? resistor can replace capacitor c9. if a dynamic control signal is used to oper ate the pfctimer pin, the recommended c9 capacitor value is 1 nf. this value results in the shortest pfctimer pin response time to an external control signal. correct timing is important if an external dynamic signal is used to override the pfc, especially when switching on the pfc. operate v pfctimer close to 4.6 v (v th(off)pfctimer(max) ) when the pfc is switched off. it minimizes the external driver current required to override the pfc and it allows a fast response to the external pfc switch-on signal. to force pfc on, sink current out of pfctimer pin: (21) to force a pfc switch-off, sour ce current into pfctimer pin: fig 17. pfctimer pin waveform w w g 3 ) & v z r i i w w 3 ) & v w d w x v d f w l y h r q k r o g 9 3 ) & 7 , 0 ( 5 3 r 3 ) & v z r i i 3 r 3 r 3 ) & v z r q d d d i pfctimer 4.7 ? a ?
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 27 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller (22) figure 18 shows two example circuits to overrule the auto pfc on/off functionality. the optocoupler transistor operates as a current source. the constant current through the optocoupler diode determines its output transistor current setting. both examples can handle optocoupler dark current up to 10 ? a. 7. protections 7.1 vosense overvolt age protection (ovp) v bus overshoot occurs on c4 at the initial star t-up and in case of large load steps. the relative slow response of the pfc control loop causes this overvoltage. the pfc control loop response must be slow to guarantee a good power factor and mhr performance. the vosense pin ovp limits the overvoltage on c4. if v ovp(vosense) is triggered, the pfc mosfet is swit ched off immediately regardless of the on-time setting. the switching of the pfc mosfet is inhibited until v vosense < 2.62 v. ovp is triggered when the resistor between the vosense pin and ground is open (due to a fault). the maximum bus voltage v bus(max) during overshoot is: (23) where: ? v bus(avg)pfcon is the average bus voltage when the pfc is on. i pfctimer v th off ?? pfctimer max ?? r k pfctimer ?? min sin ----------------------------------------------------- i pfctimer 4.6 v 4 k ? ------------ - i pfctimer 1.15 ma ? ?? ? ? a. force pfc on b. force pfc off fig 18. pfc override control examples d d d , & & q ) 3 ) & 7 , 0 ( 5 ' 0
r y h u u l g h v l j q d o 9 & & * 1 ' 5 8 8 d d d , & 3 ) & 7 , 0 ( 5 r y h u u l g h v l j q d o 9 & & * 1 ' & q ) 5 = 9 v bus max ?? v ovp vosense ?? v reg vosense ?? ----------------------------------- - v bus avg ?? pfcon ? 2.62 v 2.5 v --------------- - v bus avg ?? pfcon ? == 1.048 v bus avg ?? pfcon ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 28 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 7.2 vosense open and short pin detection the vosense pin has an integrated protection circuit to detect an open and short circuited pin. the vosense pin al so senses open resistors in the voltage divider. it is not required to add an external ovp circuit for the pfc. when the pin is open, an internal current source i prot(vosense) charges the vosense pin. the pfc stops switching when v vosense >v ovp(vosense) . an internal voltage clamp limits v vosense . the same condition applies when only resistor r15 is open. the pfc is not switching when v vosense v sense(pfc)max . ocp is a cycle-by-cycle protection. to avoid false triggering of the pfc ocp by th e flyback converter switching noise, keep a margin of 100 mv. false triggering of pfc oc p causes disturbance to the ac mains input current. to suppress any external disturba nce, place a small capacitor c11 of between 100 pf and 220 pf next to the pfcsense pin. (24) the current sense resistor r7 can be calculated with equation 25 : (25) where: ? i pk(pfc)max is the maximum pfc peak current at the high output load and low mains while the pfc operates in qr mode. the maximum peak current for the pfc operating in quasi-resonant (qr) mode is calculated using equation 26 : (26) 100 pf c11 220 pf ?? r7 v sense pfc ?? max v min arg ? i pk pfc ?? max ------------------------------------------------------------ - 0.495 v0.1 v ? i pk pfc ?? max -------------------------------------- == i pk pfc ?? max 22p imax ?? 1.1 ? v mains rms ?? min --------------------------------------- - 22 p omax ?? ? total ----------------- - 1.1 ? v mains rms ?? min ---------------------------------------- - ==
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 29 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller where: ? p o(max) is the maximum output power of the flyback. ? a factor 1.1 is used to compensate the de ad time between zero-current in the pfc inductor at the end of the secondary stroke and the detection of the first valley in quasi-resonant mode. ? ? total is the expected efficiency of the total converter at maximum output power at low mains. use 90 % for the initial design. ? v mains(rms)min is the minimum rms mains input voltage.
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 30 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 8. flyback description 8.1 flyback operation modes at initial start-up, the flyback controller starts at the maximum output power. so the system starts in quasi-resonant (qr) mode. th e flyback controller passes through three operation modes from maximum to minimum output power (see figure 19 ): ? quasi-resonant (qr) mode ? discontinuous conduction mode (dcm) ? frequency reduction (fr) mode the internal demagnetization detection and va lley switching circuitry is active in all operating modes. the ssl8516t flyback controller waits until the transformer is demagnetized and at least one valley has appeared before it is magnetized again for the next cycle. fig 19. flyback operation modes fig 20. hv pin and fbaux pin d d d ) 5 ' & 0 4 5 3 ) & r q r x w s x w s r z h u ) 5 ) u h t x h q f \ 5 h g x f w l r q ' & 0 ' l v f r q w l q x r x v & r q g x f w l r q 0 r g h 4 5 4 x d v l 5 h v r q d q w o s n p l q d g m x v w i v z i e n + ] 3 ) & r i i ) % $ 8 ; * 1 ' + 9 , & 9 2 d d d 5 4 ' 7 & & 9 e x v ' 5 5 5
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 31 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the fbaux pin detects demagnetization via the auxiliary winding. the hv pin detects the bottom of the valley via the drain of the mosf et or the central tap of the primary winding. the power conversion can be calculated with equation 27 : (27) where: ? l p(fb) is the flyback transformer primary inductance ? i pk(fb) is the flyback transformer primary peak current ? f sw(fb) is the flyback controller operating frequency ? ? fb is the flyback controller efficiency l p(fb) is selected at the start of the design. i pk(fb) is regulated to meet the output power demand in qr and dcm mode. the switching frequency f sw(fb) is a result of external application parameters and ic parameters. external application parameters: ? transformer turns ratio n fb ? primary inductance l p(fb) ? drain source capacitance of the flyback switch c d(fb) ? input voltage v bus of the flyback stage ? output voltage v o ? control loop feedback signal v fbctrl ic parameters: ? oscillator setting ? peak current setting ? demagnetization detection ? valley detection 8.1.1 quasi-resonant (qr) mode the flyback operates in qr mode at high and maximum output power. the peak current control sets the output power p o . reducing i pk(fb) results in a lower p o and a higher operating frequency until f sw(fb)max is reached. qr mode can easily be recognized. the primary switching cycle starts at the bottom of the first valley and v sense(fb) >232mv. the v fbctrl pin sets the primary peak current i pk(fb) limit level v sense(fb) . p o 1 2 -- - l pfb ?? i pk fb ?? 2 f sw fb ?? ? fb ?? ? ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 32 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller in qr mode, the pfc switch-o ff timer is never started. equation 28 shows the relationship between the v sense(fb) voltage and the flyback peak current: (28) where: ? v sense(fb) varies between 232 mv and 545 mv ? i adj(fbsense) is a 2.1 ? a current source inside the ic; connected to pin fbsense ? i r20 ? v bus /r20 fig 21. v sense(fb) setting as function of v fbctrl fig 22. flyback adjustment circuit 9 ) % & 7 5 / d d d 9 v h q v h i e i pk fb ?? v r36 r36 ----------- v sense fb ?? v r29 v r30 v r31 ??? r36 -------------------------------------------------------------------------- - == i pk fb ?? v sense fb ?? i adj fbsense ?? r29 r30 + ?? i adj fbsense ?? i r20 + ?? r31 ? ? ? r36 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ = ? $ ) % 6 ( 1 6 ( * 1 ' ) % ' 5 , 9 ( 5 , & & 5 5 & 9 e x v 9 2 5 d d d 5 4 ' 7 & ' 5 & 5 5
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 33 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 8.1.2 discontinuous conduction mode (dcm) p o decreases when i pk(fb) is reduced and more than one valley is skipped. it results in f sw(fb) operating just below f sw(fb)max (130 khz). the operating mode switches from dcm to fr mode at v fbctrl equals v start(red)f (4.0 v). sometimes dcm is not reached when the selected primary inductance of the inductor is high. in this case, flyback skips dcm when it is reducing power. it jumps directly from qr mode to fr mode. in dcm, the pfc switch-off timer is not started. 8.1.3 frequency reduction and pfc on/off control at medium and low output power, i pk(fb) is fixed. the operating frequency controls p o . p o and f sw(fb) are linearly related during this type of co ntrol. in this applicat ion note, it is called operating in frequency reduction (fr) mode. the minimum switching frequency in fr mode is 0 hz. in fr mode, v fbctrl does not set the peak current. it sets the operating frequency. the minimum primary peak current i pk(fb)min through the l p(fb) is kept constant in fr mode. the ratio i pk(fb)min :i pk(fb)max mainly depends on the sense resistor r36 and r30 assuming that the core does not saturate at i pk(fb)max . decreasing the output power reduces the operating frequency. as a result of the frequency limit, more valleys are skipped. only in fr mode, f sw(fb) determines when th e pfc is on or off. fig 23. flyback frequency control d d d ) 5 ' & 0 4 5 4 5 4 x d v l 5 h v r q d q w ' & 0 ' l v f r q w l q x r x v & r q g x f w l r q 0 r g h ) 5 ) u h t x h q f \ 5 h g x f w l r q i v z i e 4 5 p l q i v z i e n + ] 9 ) % & 7 5 / 9
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 34 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 8.2 flyback protections 8.2.1 short circuit at the fbctrl pin if the fbctrl pin is shorted to ground, switching of the flyback controller is inhibited. 8.2.2 open fbctrl pin pin fbctrl connects to an internal 7 v voltage source (see figure 24 ) via an internal 13.2 k ? resistor and a series switch. when v fbctrl > 5.5 v, the series switch opens and the 13.2 k ? resistor disconnects. pin fbctrl is biased with 29 ? a i to(fbctrl) . when v fbctrl > 7.75 v, a fault is assumed. the fl yback and pfc switches are switched off and a safe restart is init iated. an internal pull-down switch on the fbctrl pin is activated during the safe restart. 8.2.3 time-out flyback control loop a time-out function is set using resistor r2 7 and capacitor c23 to protect against the following faults: ? output short circuit at initial start-up ? open flyback control loop the time-out protection initiates a safe restart.
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 35 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller a noise filter (c17 = 220 pf; r21 = 10 ? ) located close to pin fbctrl avoids interference by pfc mosfet switching or hf noise (e.g. gsm phone). resistor r27 and capacitor c23 set the time delay for v fbctrl to reach 7.75 v. resistor r27 is required to separate the relatively high-v alue time-out capacitor c23 from the control loop response. the value of resistor r27 must be > 30 k ? . the flyback time-out time t to(fb) can be calculated with equation 29 : (29) where: ? ? v to(fbctrl) =v to(fbctrl)trip ? v to(fbctrl)en =7.75 ? 5.5 = 2.25 v if the flyback time-out protection is not required (e.g. for testing or debugging purposes), it can be disabled. place a 180 k ? resistor between pin fbctrl and ground. a. circuit diagram b. timing diagram fig 24. flyback time-out protection ) % & 7 5 / ? $ n
5 5 & 9 9 9 w l p h r x w & d d d d d d 9 9 9 ) % & 7 5 / r x w s x w y r o w d j h w d u j h w r x w s x w y r o w d j h u h d f k h g z l w k l q w l p h r x w w l p h u h v w d u w w d u j h w r x w s x w y r o w d j h q r w u h d f k h g z l w k l q w l p h r x w w l p h t to fb ?? c23 ? v to fbctrl ?? i to fbctrl ?? --------------------------------- ? r27 c23 i to fbctrl ?? r27 ? v to fbctrl ?? en ------------------------------------------ ?? ?? ln ?? ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 36 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 8.2.4 flyback overvoltage protection (ovp) to disable both controllers when overvoltage is detected at the output of the flyback, the ic has an internal ovp circuit. the voltage on the flyback transformer secondary winding during the secondary stroke is a reflection of the output voltage plus the voltage of the secondary rectifier. during the secondary stroke, the voltage on the auxiliary v aux(t1) winding equals: (30) where: ? v o is the output voltage ? v rectifier is the voltage across the ou tput rectifier when conducting ? n aux(fb) is the number of auxiliary turns ? n s(fb) is the number of secondary turns the total series resistance r23 + r41 loca ted between the auxilia ry winding and the fbaux pin converts v aux(t1) to current in pin fbaux. an internal integrator filters noise and spikes . the output of the integrator connects to a counter. the counter prevents false ovp detection which can occur during esd or lightning events. the ovp condition is met when i fbaux >300 ? a. if the internal inte grator detects ovp, the counter increa ses by one. if ovp is detected during the next switching cycle, the counter increases by one again. if no ovp is detected during the next switching cycle, the counter decreases by two. (the minimum value is zero.) if the counter reaches six, the ic assumes a true overvoltage. both converters are switched off immediately and a safe restart is initiated. r ovp = r23 + r41 fig 25. flyback ovp circuit v aux t1 ?? v o v rectifier + ?? n aux fb ?? n sfb ?? ------------------ - ? = ) % $ 8 ; * 1 ' + 9 , & 9 2 d d d 5 4 ' 7 & & 9 e x v ' 5 5 5
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 37 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the ovp level can be calculated with equation 31 : (31) where: ? n s(fb) is the number of turns on the secondary winding ? n aux(fb) is the number of turns on the fl yback transformer auxiliary winding ? v o(ovp) is the output voltage ovp level ? v rectifier is the forward voltage of the secondary rectifier (0.6 v for diode) ? v clamp(fbaux) is pin fbaux positive clamp voltage 0.92 v ? i ovp(fbaux) is the ovp protection level ? r23 is 10 k ? placed close to the ic pin to avoid ovp triggering in normal operation, take the tolerances on i ovp(fbaux) into account for v o(ovp) calculation. the maximum series resistance calculation is based on the demagnetization threshold. (32) keep some margin and keep r ovp <650k ? . higher values can cause slow output voltage rise during initial start-up which can trigger the time-out protection because the demagnetization function is disturbed. r23 r41 + n aux fb ?? n sfb ?? ------------------ - ?? ?? v oovp ?? v rectifier + ?? v clamp fbaux ?? ? ? i ovp fbaux ?? ------------------------------------------------------------------------------------------------------------------------ - = r41 n aux fb ?? n sfb ?? ------------------ - ?? ?? v oovp ?? v rectifier + ?? 0.92 ? ? 300 ? a ----------------------------------------------------------------------------------------------- 10 k ? ? = ? r ovp v th comp ?? fbaux min ?? i prot fbaux ?? min ------------------------------------------------- 60 mv 65 na ---------------- 923 k ? == ?
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 38 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 8.2.5 overpower protection (opp) the ssl8516t is a fixed boost pfc controller. so the opp is not required when using the default application where v bus(avg)pfcon is fixed over the full mains voltage range. diode d7 and resistor r23 disable the opp (see figure 26 ). the current flowing out of pin fbaux is limited to < 100 ? a. fig 26. opp level adjustment d d d , ) % $ 8 ; ? $ 9 ) % 6 ( 1 6 ( p 9
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 39 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 9. large signal component values calculation ta b l e 3 shows the initial requirements of an led driver as example. 9.1 bus capacitor for the bus capacitor value calculation, several constraints apply: ? voltage rating ? ovp level on the vosense pin ? holdup time ? auto pfc on/off with load step support 9.1.1 voltage rating the target is to use a single 450 v bus capacitor c4. ? ? ? the minimum bus capacitance due to the allowed voltage ripple based on the c4 voltage rating is: (33) table 3. initial design requirements requirement symbol choice example low input voltage v ac(rms)min 90 v (ac) 100 v; ? 10 % margin high input voltage v ac(rms)max 305 v (ac) 277 v; +10 % margin thd at 305 v (ac) can be compromised when a 450 v bus capacitor is used output voltage v o(min) 16 v v o(max) :v o(min) =3:1 v o(max) 48 v output current i o(min) 160 ma 75 w; 10 % dimmable led driver i o(max) 1.6 a holdup time t holdup 0 ms lower output capacitance and bus capacitance can be used when no hold up time is required flyback mosfet voltage rating v ds(fb)max 800 v allows high n fb v o : ? lower voltage stress on the secondary rectifier ? less turn on losses due to deeper valley fast transient support - no (cc output) a smaller c bus can be used when no transient support is required when pfc is switched off v c4 max ?? 450 v = v bus avg ?? pfcon v mains rms ?? max 23052431 v == ? = v bus ripple ?? pp max ?? 2v c4 max ?? v bus avg ?? pfcon ? ?? 38 v == c4 rating v omax ?? i omax ?? ? 2 ? f ac min ?? v bus ripple ?? pp max ?? v bus avg ?? pfcon ? total ?? ? ? ? --------------------------------------------------------------------------------------------------------------------------------------------- = c4 rating 48 1.6 ? 2 ? 50 38 431 0.9 ?? ? ? ? -------------------------------------------------------- - 16.6 ? f == ?
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 40 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller where: ? f ac(min) is the minimum mains frequency 50 hz ? ? total is the total efficiency 9.1.2 ovp level on the vosense pin the minimum bus capacitance due to ovp on the vosense pin is: (34) 9.1.3 holdup time the minimum capacitance due to the holdup time requirement is: (35) where: ? v bus(holdup)min is the minimum bus voltage at whic h the flyback stage can still transfer p o(max) , typically between 60 v and 100 v ? ? fb is the flyback efficiency (assumption: 0.95) 9.1.4 auto pfc on/off here is a rule of thumb for the minimum bus capacitance supporting auto pfc on/off function and wide mains applications with certain load step requirements: ? constant current led drivers 0.3 ? f/w (smooth load steps): ? constant voltage led drivers 1.0 ? f/w (large load steps): transient step response support is not required (see ta b l e 3 ): (36) (37) c4 ovp v omax ?? i omax ?? ? 4 ? f ac min ?? v bus avg ?? pfcon 2 ? total ?? ? ? ---------------------------------------------------------------------------------------------- v reg vosense ?? v ovp vosense ?? v reg vosense ?? ? ----------------------------------------------------------------------------- ? = c4 ovp 48 1.6 ? 4 ? 50 431 2 0.9 ?? ? ? ------------------------------------------------ - 2.5 2.62 2.5 ? ----------------------- - 15.3 ? f = ? = ? c4 holup 2v omax ?? i omax ?? ?? ? fb ---------------------------------------------- t holdup ? v bus avg ?? pfcon v bus ripple ?? pp max ?? 2 -------------------------------------------- ? ?? ?? 2 v bus holdup ?? min 2 ? -------------------------------------------------------------------------------------------------------------------------------------------- = c4 holdup 2481.6 ?? 0.95 ------------------------- 0 ? 431 38 2 ----- - ? ?? ?? 2 100 2 ? ---------------------------------------------- 0 ? f = = ? c4 pfconoff 0.3 ? fp omax ?? ? = c4 pfconoff 1.0 ? fp omax ?? ? = c4 pfconoff 0.3 ? fp omax ?? 0.3 48 1.6 23 ? f = ?? = ? = ? c4 max c4 ripple , c4 ovp , c4 holdup , c4 pfconoff ?? ? c4 max 16.6 , 15.3 , 0 , 23 ?? 23 ? f ? ??
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 41 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the value chosen for capacitor c4 is 22 ? f. the recalculated peak-to-peak bus voltage ri pple with the selected bus capacitor c4 is: (38) the final bus voltage with the selected bus capacitor c4 can be set: (39) 9.2 pfc inductance the minimum pfc switching frequency requirement at full load determines the maximum pfc inductance. at low line, the primary stroke is dominant and at high mains the secondary stroke is dominant, both conditions must be checked: (40) where: ? f sw(pfc)min (minimum pfc switching frequency) = 20 khz (41) (42) 9.3 reflected output voltage the reflected output voltage v r (equals n fb v o ) is a compromise between the flyback mosfet voltage rating v ds(fb)max and secondary rectifier reverse voltage rating. ? high n fb : more voltage stress on the flyback mosfet ? low n fb : more voltage stress on secondary rectifier the leakage inductance of the flyback tran sformer generates a ringing voltage on the drain at switch-off. allow at least 20 % of the v ds(fb)max margin as starting point. v bus ripple ?? pp p omax ?? 2 ? f ac min ?? c4 v bus avg ?? pfcon ? total ?? ? ? ? ------------------------------------------------------------------------------------------------------- - = v bus ripple ?? pp 48 1.6 ? 2 ? 50 22 ? f 431 0.9 ?? ? ? ? ------------------------------------------------------------------ - 28.6 v == ? v bus nom ?? v c4 max ?? v bus ripple ?? pp 2 -------------------------------- ? 450 28.6 2 ---------- ? 435 v == = l pfc lowline ?? v mains rms ?? min 2 v bus nom ?? 2v mains rms ?? min ? ? ?? ? 2f sw pfc ?? min p omax ?? ? total ----------------- - v bus nom ?? ??? -------------------------------------------------------------------------------------------------------------------------- - = l pfc lowline ?? 90 2 435 2 90 ? ? ?? ? 220 khz 48 1.6 ? 0.9 ----------------- - 435 ??? ------------------------------------------------------------- - 1.679 mh == ? l pfc highline ?? v mains rms ?? max 2 v bus nom ?? 2v mains rms ?? max ? ? ?? ? 2f sw pfc ?? min p omax ?? ? total ----------------- - v bus nom ?? ??? ---------------------------------------------------------------------------------------------------------------------------- = l pfc highline ?? 300 2 435 2 300 ? ? ?? ? 220 khz 48 1.6 ? 0.9 ----------------- - 435 ??? ------------------------------------------------------------- - 803 ? h == ? l pfc min l pfc lowline ?? , l pfc highline ?? ?? 803 ? h ??
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 42 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the reflected output voltage v r is super-imposed on the v bus during the secondary stroke. (43) where: ? v ds(fb)max is the flyback mosfet maximum drain source voltage ? v bus(max) is the maximum bus voltage ? v r is the reflected output voltage ? v o(max) is the maximum output voltage the peak voltage during ringing in applications can be minimized with the flyback clamp circuit with diode d4, resistor r16, and capacitor c12. 9.3.1 primary flyback inductance (l p(fb) ) at full power, the system must operate in qr mode at the highest efficiency possible. the results is an optimized transformer design with accompanying i sat(fb) , l p(fb) , and f sw(fb)qr(min) . so, the flyback inductance is selected based on the desired minimum operating frequency in qr mode at p o(max) . fig 27. flyback mosfet drain voltage v ds(fb) with ringing d d d w l p h 9 e x v 9 u 9 e x v 9 u 9 e x v 9 e x v 9 e x v 9 u 9 9 ' 6 i e 9 0.8 v ds fb ?? max ? v bus max ?? v r + v bus max ?? n fb v omax ?? ? + == v bus max ?? n pfb ?? n sfb ?? ------------- - v omax ?? ? + =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 43 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller the equation for the primary flyback inductance is: (44) where: ? f sw(fb)qr(min) minimum flyback switching frequency in qr mode ? ? fb is the flyback controller efficiency, typically 0.95 ? v bus(min) is the expected minimum bus voltage ? n fb is flyback turns ratio n p(fb) /n s(fb) ? v o is the output voltage ? p o(max) is the maximum output power ? c d(fb) is the total capacitance on the drain of the flyback switch to ensure that the pfc is on at p o(pfc)swon , the l p(fb) must not exceed the value l p(fb)max when the auto pfc on/off function is used (see section 6.6 ). (45) fig 28. minimum frequency in qr mode d d d ) 5 ' & 0 4 5 4 5 4 x d v l 5 h v r q d q w ' & 0 ' l v f r q w l q x r x v & r q g x f w l r q 0 r g h ) 5 ) u h t x h q f \ 5 h g x f w l r q i v z i e 4 5 p l q i v z i e n + ] 9 ) % & 7 5 / 9 l pfb ?? = 1 2p omax ?? f sw fb ?? qr min ?? ?? ? fb -------------------------------------------------------------- - ?? ?? ?? 1 v bus min ?? --------------------- - 1 n fb v o -------------- + ?? ?? f sw fb ?? qr min ?? ? c dfb ?? ?? + ? 2 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - l pfb ?? max = 1 273 khz p opfc ?? swon ?? ? fb ----------------------------------------------------------- - ?? ?? ?? 1 v mains rms ?? min 2 ? --------------------------------------------- 1 n fb v o -------------- + ?? ?? ?? f sw fb ?? qr min ?? ? c dfb ?? ?? + ? 2 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 44 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller where: ? v mains(rms)min is the minimum mains voltage (ac) ? v o(min) is the minimum output voltage ? ? fb is the flyback controller efficiency, typically 0.95 ? n fb is flyback turns ratio n p(fb) /n s(fb) ? p o(pfc)swon is the output power at which the pfc must be enabled ? c d(fb) is the total capacitance on the drain of the flyback switch the effects of the primary inductance l p(fb) are: ? high value: small pfc s witch on/off hysteresis ? low value: lower efficiency du e to flyback switching losses 9.3.2 flyback peak current (i pk(fb) ) the output power p o is calculated with equation 46 : (46) in qr and dcm modes, v fbctrl sets the flyback peak current i pk(fb) ; f sw(fb) is a result. in fr mode, v fbctrl sets f sw(fb) ; i pk(fb) is fixed at its minimum level i pk(fb)min . 9.3.2.1 maximum flyback peak current (i pk(fb)max ) to prevent saturation of the flyback transformer, the overcurrent protection (ocp) limits i pk(fb) . a saturated core deteriorates the overall system performance. saturation causes more stress, emi, and, in the worst case, a system failure. (47) where: ? n p(fb) is number of primary turns ? b max is maximum flux density at ex pected high operating temperature ? a e is effective core area the flyback transformer must never saturate, not even at high temperatures. to avoid saturation due to component spread, a margin of minimal 10 % must also be applied. (48) 9.3.2.2 minimum flyback peak current (i pk(fb)min ) the automatic pfc on/off function is based on f sw(fb) . when the automati c on/off function is used, equation 49 applies: (49) p o 1 2 -- - l pfb ?? i pk fb ?? 2 f sw fb ?? ? fb ?? ? ? = i sat fb ?? n pfb ?? b max a e ?? l pfb ?? ---------------------------------------- - = 0.9 i sat fb ?? ? i pk fb ?? max ? p o pfc ?? on 1 2 -- - l pfb ?? i pk fb ?? min 2 f sw fb ?? swon pfc ?? ? fb ?? ? ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 45 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller i pk(fb)min can be calculated with equation 50 : (50) where: ? f sw(fb)swon(pfc) =73khz the output power level p o(pfc)swoff at which the pfc switches off, is: (51) where: ? f sw(fb)swoff(pfc) =53khz furthermore, the ratio between i pk(fb)max and i pk(fb(min) cannot be lower than 2.35: (52) 9.3.3 flyback adjust by fbsense pin circuit the fbsense pin functionality is: ? set i pk(fb)max ? set i pk(fb)min resistor r29 and capacitor c19 prevent that the fbsense pin is charged negative because of disturbances on the sense resistor r36. i pk fb ?? min 2p o pfc ?? on ? l pfb ?? f sw fb ?? swon pfc ?? ? fb ?? -------------------------------------------------------------------- - = p o pfc ?? swoff 1 2 -- - l pfb ?? i pk fb ?? min 2 f sw fb ?? swoff pfc ?? ? fb ?? ? ? = i pk fb ?? max i pk fb ?? min v sense fb ?? max v sense fb ?? min ------------------------------ - ? ? i pk fb ?? max i pk fb ?? min 545 mv 232 mv ------------------- i pk fb ?? max i pk fb ?? min ---------------------- - 2.35 ? ? ? ? ? fig 29. flyback adjustment circuit $ ) % 6 ( 1 6 ( * 1 ' ) % ' 5 , 9 ( 5 , & & 5 5 & 9 e x v 9 2 5 d d d 5 4 ' 7 & ' 5 & 5 5
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 46 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 9.3.3.1 flyback current sense resistor r36 the sense resistor r36 can be calculated with equation 53 : (53) 9.3.3.2 fbsense noise filter resistor r29 and capacitor c19 the value of resistor r29 is between 680 ? and 2.2 k ? . the purpose of resistor r29 is to prevent that capacitor c19 is charged due to negative voltage spikes on resistor r36. a commonly used time constant for resistor r29 and capacitor c19 is approximately 220 ns. the filter capacitor at th e fbsense pin can be calculated with equation 54 : (54) the tolerance of capacitor c19 must be 10 % maximum. this tolera nce limits the impact on the overall spreading for the p o(pfc)swon and p o(pfc)swoff levels. 9.3.3.3 fbsense series resistance r s(fbsense) the total series resistance r s(fbsense) between the fbsense pin and sense resistor r36 determines the static offset voltage on the fbsense pin. r s(fbsense) is used to adjust the ratio between i pk(fb)min and i pk(fb)max . (55) (56) where: ? i adj(fbsense) is the 2.1 ? a internal current source on the fbsense pin 9.3.4 flyback switch-off delay compensation resistors r20 and r31 are intended to compensate the sum of these delays: ? switch-off internal delay time t d(fbdriver) = 80 ns of the ic ? mosfet switch-off delay time t d(mosfet)off , typically 60 ns ? delay time caused by resi stor r29 and capacitor c19 if these delay times are not compensated, they lead to an increased i pk(fb) value at a high v bus . (57) the increase of i pk(fb) depends on v bus : (58) r36 v sense fb ?? max v sense fb ?? min ? i pk fb ?? max i pk fb ?? min ? ------------------------------------------------------------------- - 545 mv 232 mv ? i pk fb ?? max i pk fb ?? min ? --------------------------------------------------- 313 mv i pk fb ?? max i pk fb ?? min ? --------------------------------------------------- === c19 220 ns r29 ---------------- = r s fbsense ?? r29 r30 r31 ++ = r s fbsense ?? i pk fb ?? max v sense fb ?? min i pk fb ?? min v sense fb ?? max ? ? ? i adj fbsense ?? i pk fb ?? max i pk fb ?? min ? ?? ? -------------------------------------------------------------------------------------------------------------------------- = t dfb ?? swoff t d fbdriver ?? t d mosfet ?? off r29 c19 ? ++ = ? i pk fb ?? v bus l pfb ?? ------------- t dfb ?? swoff ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 47 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller ? i pk(fb) results in a voltage on resistor r36 wh ich must be compensa ted as a function of v bus by i r20 through resistor r31: (59) v bus drops out of the equation: (60) r31 can be calculated once r20 is selected. (61) r20 sets the current i r20 through resistor r31. choose i r20 >3 ? i adj(fbsense) : assuming : (62) to meet the rated resistor voltage, r20 is typically constructed with several 0805 resistors in series. remark: always verify the actual t d(mosfet)swoff in the application prototype because of different mosfet types and diff erent gate discharge resistors. fig 30. i pk(fb)min increase due to a switch-off delay d d d w l p h 9 e x v 9 9 e x v 9 , s n i e p l q g 9 g w i r20 r31 ?? i pk fb ?? r36 ? v bus r20 ---------- r31 ?? i pk fb ?? r36 ? = ? = v bus r20 ---------- r31 ? v bus l pfb ?? ------------- t dfb ?? swoff r36 ?? = ? r31 r20 --------- - t dfb ?? swoff l pfb ?? ---------------------- - r36 ? = r31 t dfb ?? swoff l pfb ?? ---------------------- - r20 r36 ?? = v bus v fbsense ? r20 v bus min ?? 3i adj fbsense ?? ? ---------------------------------------- ??
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 48 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 9.3.5 flyback soft-start soft-start is implemented using the rc network connected to the fbsense pin. to ensure that v start(soft)fb is reached and flyback start-up is enabled, the sum of resistors r29, r30, and r31 must be > 15 k ? . the flyback soft-start t start(soft)fb must range between 5 ms and 10 ms. furthermore, t start(soft)fb must be longer than the pfc soft-start time t start(soft)pfc . (63) (64) t start soft ?? fb t start soft ?? pfc ? t start soft ?? fb 3r30r31 + ?? c20 ?? 7 ms ? =
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 49 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 10. pcb layout considerations a good layout is an important part of the final design. it minimizes many kinds of disturbances and makes the overall performan ce more robust with less risk of emi. guidelines for the pcb layout are: ? separate large signal grounds from small signal grounds (pfc, fb, and ic). ? reduce the pcb area within the indicated large signal current loops (pfc inductor and fb inductor currents) to a minimum. each indicated large signal loop has its own color in figure 1 and figure 2 . make the copper tracks as short and as wide as possible. ? the connection between both mosfets (pfc and flyback) and the ic driver outputs must be as short as possible. to minimize inductance, use wide tracks. increase the distance between the copper tracks and/or use a separate guided ground track for both connections. the separated guided ground track minimizes the coupling between the pfcdriver and fbdri ver signals. if it is impossible to place the mosfet and the ic close to each other, a circuit, like the one in figure 31 , can be added. ? the power ground and small signal ground are only connected with one short copper track (make this track as short and as wide as possible). preferably, it should become one spot (connection between ic ground and star ground at the bus capacitor). ? use a ground shield underneath the ic, connect this ground shield to the gnd pin of the ic. ? place all series connected resistors that are fi xed to an ic pin as close as possible to that pin. ? heat sink can carry hf currents. connec t heat sinks which are connected to the nearest corresponding ground signal of the component. make this connection as short as possible. connect the heat sink of q1 to the ground pfc and the heat sink of q3 to the ground fb. in typical applications, all primary components are often mounted on a single heat sink. if so, make one wide copper track that connects all these grounds to each other. combine in this copper track th e ground of the pi filt er (capacitors c1 and c2). ? place capacitors c10 (vosense), c17 (fbctrl), c19 (fbsense), and c11 (pfcsense) (in order of priority) as clos e as possible to the ic. reduce coupling between the pfc switching signals (p fcdriver and pfcaux) and the flyback sense signals (fbsense and fbctrl) as mu ch as possible. t he coupling reduction minimizes the risk of electromagnetic interference and audible noise.
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 50 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller fig 31. mosfet local turn-off circuit d d d , & * 1 ' ' 5 , 9 ( 5
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 51 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 11. abbreviations 12. references [1] ssl8516t data sheet ? greenchip pfc and flyback controller [2] um10776 user manual ? ssl8516db1195 75 w 1.6 a dimmable led driver table 4. abbreviations acronym description ac alternate current dc direct current dcm discontinuous conduction mode emi electromagnet ic interference fr frequency reduction gnd ground gsm global system for mobile communications hv high-voltage ic integrated circuit iec international electrotechnical commission led light emitting diodes mhr mains harmonics reduction mosfet metal oxide semiconductor field effect transistor ntc negative temperature coefficient ocp overcurrent protection opp overpower protection otp overtemperature protection ovp overvoltage protection pcb printed-circuit board pf power factor pfc power factor converter/controller/correction qr quasi-resonant rms root mean square smps switched mode power supply so small outline soi silicon-on-insulator ssl solid-state lighting thd total harmonic distortion uvlo undervoltage lockout zcs zero current signal
an11486 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. application note rev. 1 ? 17 july 2014 52 of 53 nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller 13. legal information 13.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 13.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconducto rs products, and nxp semiconductors accepts no liability for any assistance wi th applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. evaluation products ? this product is provided on an ?as is? and ?with all faults? basis for evaluati on purposes only. nxp semico nductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. the entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. in no event shall nxp semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. notwithstanding any damages that customer might incur for any reason whatsoever (including without limitat ion, all damages referenced above and all direct or general damages), the entire liability of nxp semiconductors, its affiliates and their suppliers and custom er?s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (us$5.00) . the foregoing limitations, exclusions and disclaimers shall apply to the ma ximum extent permitted by applicable law, even if any remedy fails of its essential purpose. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 13.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp semiconductors n.v.
nxp semiconductors an11486 greenchip ssl8516t pfc and flyback controller ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 july 2014 document identifier: an11486 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 14. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 system features . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 pfc features . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 flyback features . . . . . . . . . . . . . . . . . . . . . . . . 4 3 ssl8516t schematic . . . . . . . . . . . . . . . . . . . . . 5 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 pinning diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . 7 5 system description and calculation. . . . . . . . 10 5.1 pfc and flyback start conditions . . . . . . . . . . 10 5.2 initial start-up sequence . . . . . . . . . . . . . . . . . 10 5.3 v cc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 mains voltage sensing and brownout . . . . . . . 13 5.4.1 discharging the mains input capacitor . . . . . . 13 5.4.2 brownout voltage adjustment . . . . . . . . . . . . . 14 5.5 internal overtemperature protection (otp). . 14 5.6 latch pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . 15 6 pfc description . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 pfc output voltage and voltage control . . . . . 16 6.2 mains current harmonics (mhr) . . . . . . . . . . 18 6.2.1 residual c1 voltage . . . . . . . . . . . . . . . . . . . . 18 6.2.2 pfc inductor energy too low . . . . . . . . . . . . . 18 6.2.3 bus voltage ripple . . . . . . . . . . . . . . . . . . . . . . 19 6.2.4 valley hopping . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.5 mhr improvement guidelines. . . . . . . . . . . . . 19 6.3 pfc output voltage . . . . . . . . . . . . . . . . . . . . . 20 6.4 calculation of the pfc soft-start components 21 6.5 pfc demagnetization and valley detection . . 21 6.5.1 pfcaux winding and circuit design . . . . . . . . 22 6.6 pfc on/off. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6.1 pfctimer pin circuit . . . . . . . . . . . . . . . . . . . 25 6.6.1.1 automatic pfc on/off . . . . . . . . . . . . . . . . . . . 25 6.6.1.2 overruling autom atic pfc on/off . . . . . . . . . . 26 7 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 vosense overvoltage protection (ovp) . . . 27 7.2 vosense open and short pin detection . . . . 28 7.3 vinsense open pin detection . . . . . . . . . . . . 28 7.4 overcurrent protection (ocp) . . . . . . . . . . . . 28 8 flyback description . . . . . . . . . . . . . . . . . . . . . 30 8.1 flyback operation modes . . . . . . . . . . . . . . . . 30 8.1.1 quasi-resonant (qr) mode . . . . . . . . . . . . . . 31 8.1.2 discontinuous conduction mode (dcm) . . . . 33 8.1.3 frequency reduction and pfc on/off control . 33 8.2 flyback protections . . . . . . . . . . . . . . . . . . . . 34 8.2.1 short circuit at the fbctrl pin . . . . . . . . . . . 34 8.2.2 open fbctrl pin . . . . . . . . . . . . . . . . . . . . . 34 8.2.3 time-out flyback control loop . . . . . . . . . . . . . 34 8.2.4 flyback overvoltage protection (ovp) . . . . . 36 8.2.5 overpower protection (opp). . . . . . . . . . . . . 38 9 large signal component values calculation. 39 9.1 bus capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.1 voltage rating . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.2 ovp level on the vosense pin . . . . . . . . . . 40 9.1.3 holdup time . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4 auto pfc on/off . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 pfc inductance . . . . . . . . . . . . . . . . . . . . . . . 41 9.3 reflected output voltage . . . . . . . . . . . . . . . . 41 9.3.1 primary fly back inductance (l p(fb) ) . . . . . . . . . 42 9.3.2 flyback peak current (i pk(fb) ) . . . . . . . . . . . . . 44 9.3.2.1 maximum fly back peak current (i pk(fb)max ) . . . 44 9.3.2.2 minimum flyback peak current (i pk(fb)min ) . . . . 44 9.3.3 flyback adjust by fbsense pin circuit . . . . . 45 9.3.3.1 flyback current sense re sistor r36 . . . . . . . . 46 9.3.3.2 fbsense noise filter resistor r29 and capacitor c19 . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3.3.3 fbsense series resistance r s(fbsense) . . . . 46 9.3.4 flyback switch-off delay compensation . . . . . 46 9.3.5 flyback soft-start . . . . . . . . . . . . . . . . . . . . . . 48 10 pcb layout considerations . . . . . . . . . . . . . . 49 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13 legal information . . . . . . . . . . . . . . . . . . . . . . 52 13.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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